1. Field of the Invention
The present invention relates to an electrically programmable nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device packaged at high density.
2. Description of the Related Art
A surge in the need for small-sized, large-capacity nonvolatile semiconductor memory devices causes attention to be focused on NAND-type flash memories, which are expectable to achieve high integration and mass storage.
Proceeding high integration and mass storage associated with the NAND-type flash memory requires a reduction in design rule. The reduction in design rule requires finer pattering of wiring patterns and so forth. Realizing finer pattering of wiring patterns and so forth requires extremely sophisticated processing technologies and makes it difficult to achieve the reduction in design rule.
In recent years, a number of semiconductor memory devices including memory cells arranged in three dimensions have been proposed to increase the degree of integration. (See JP 2003-078044A, and Masuoka et al., “Novel Ultrahigh-Density Flash Memory With a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 4, pp. 945-951, April 2003).
Many of the semiconductor memory devices of prior art including memory cells arranged in three dimensions require plural photo-etching processes (hereinafter referred to as “PEP”: Processes for patterning with the use of the so-called lithography step using photoresist and the steps of processing such as etching) per layer in the memory cell portion. A photo-etching process with the minimum line width in the design rule is herein referred to as a “critical PEP”. A photo-etching process with a larger line width than the minimum line width in the design rule is herein referred to as a “rough PEP”. The semiconductor memory device of conventional art including memory cells arranged in three dimensions requires three or more critical PEPs per layer in the memory cell portion. Many of the semiconductor memory devices of conventional art comprise simply stacked memory cells, which inevitably increase the cost on achievement of the three-dimensionality.
One of the semiconductor memory devices of conventional art including memory cells arranged in three dimensions is a semiconductor memory device including cylinder-structured transistors (SGT: Surrounding Gate Transistor) (JP 2003-078044A). The semiconductor memory device including the cylinder-structured transistors (SGT) is produced through processes of forming channel (body) portions in stacked memory transistors in the shape of pillars, and then forming on sides a film of polysilicon to be turned into gate electrodes. Therefore, the structure seen from right above is a skewered structure.
In the semiconductor memory device thus structured, if an ON-state achievable electric field is applied to gate electrodes, each of the gate electrodes causes a variation in channel to be formed. Therefore, variations in resistance arise, leaving insufficient controllability and stability. In addition, a channel formed in a semiconductor region tends to have a higher resistance.
Further, a narrowed interval between the gate electrodes for the purpose of high integration increases the capacity between the gate electrodes and may increase the disturbance failure possibly.